AMD has launched EPYC Venice, the first x86 server processor built on TSMC’s 2-nanometer process, alongside the Helios rack-scale AI system, at its Advancing AI event in San Francisco on July 22 and 23. Microsoft committed to deploying Helios across Azure in the second half of 2026, giving the platform a hyperscaler anchor before general availability.
Venice is AMD’s first server CPU on the Zen 6 architecture, scaling to 256 cores against the 192-core ceiling of the current Turin generation, a 33 percent increase. The chip supports PCIe 6.0 and 16-channel DDR5 memory, and AMD claims more than 70 percent higher performance and efficiency than its Zen 5 predecessor.
Helios is the company’s answer to Nvidia’s rack-scale systems. Each rack pairs 72 Instinct MI455X accelerators with Venice host CPUs and AMD Pensando networking, carrying a combined 31 terabytes of HBM4 memory and delivering up to 2.9 exaflops of FP4 compute and 1.4 exaflops at FP8. Where Nvidia’s Vera Rubin platform extends a vertically integrated stack from silicon to orchestration software, AMD is betting on open standards: Helios networking runs on Ultra Ethernet Consortium and UALink fabrics, the rack follows the Open Compute Project’s Open Rack Wide design, and the software layer is AMD’s open-source ROCm stack with support for PyTorch, vLLM, and Triton.
Microsoft’s commitment gives that bet early commercial validation. Azure plans three new virtual machine families on the hardware: the ND MI455X v7 series for inference workloads, built on full Helios racks; the HDv2, a Venice-based instance with nearly 500 physical cores and 4 terabytes of memory aimed at data preparation and agent orchestration; and the HXv2 for chip design and scientific computing. Microsoft has not given pricing or a specific launch date beyond the second-half window.
The launch is AMD’s most direct attempt yet to convert the AI buildout’s scale into share gains. Hyperscalers projected to spend around $600 billion on AI infrastructure in 2026 have an interest in a credible second source of rack-scale systems, both for price leverage against Nvidia and for supply resilience while accelerator demand outruns production. An open-standards rack that slots into OCP data center designs lowers the switching cost that has kept that spending concentrated on one vendor.
Venice also answers Intel, which brought its 18A process to the data center in June with the 288-core Xeon 6+ Clearwater Forest and claimed a 30 percent per-thread advantage over the current EPYC generation. AMD’s 2-nanometer response arrives as every point of efficiency carries more weight: power availability, not chip supply, has become the binding constraint on data center expansion in the largest US markets.
Sources: TechPowerUp, TechTimes, Windows News
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By the Control Plane Editorial Team